; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN1 %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN2 %s

define amdgpu_kernel void @atomic_add_i64_offset(ptr %out, i64 %in) {
; GCN1-LABEL: atomic_add_i64_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v0, s2
; GCN1-NEXT:    v_mov_b32_e32 v1, s3
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_add_x2 v[2:3], v[0:1]
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_add_i64_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v0, s2
; GCN2-NEXT:    v_mov_b32_e32 v1, s3
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_add_x2 v[2:3], v[0:1]
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    s_endpgm
entry:
  %gep = getelementptr i64, ptr %out, i64 4
  %tmp0 = atomicrmw volatile add ptr %gep, i64 %in seq_cst
  ret void
}

define amdgpu_kernel void @atomic_add_i64_ret_offset(ptr %out, ptr %out2, i64 %in) {
; GCN1-LABEL: atomic_add_i64_ret_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xd
; GCN1-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_add_x2 v[0:1], v[2:3], v[0:1] glc
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_add_i64_ret_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x34
; GCN2-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_add_x2 v[0:1], v[2:3], v[0:1] glc
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %gep = getelementptr i64, ptr %out, i64 4
  %tmp0 = atomicrmw volatile add ptr %gep, i64 %in seq_cst
  store i64 %tmp0, ptr %out2
  ret void
}

define amdgpu_kernel void @atomic_add_i64_addr64_offset(ptr %out, i64 %in, i64 %index) {
; GCN1-LABEL: atomic_add_i64_addr64_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN1-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s6
; GCN1-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN1-NEXT:    s_add_u32 s0, s4, s0
; GCN1-NEXT:    s_addc_u32 s1, s5, s1
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v1, s7
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_add_x2 v[2:3], v[0:1]
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_add_i64_addr64_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
; GCN2-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s6
; GCN2-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN2-NEXT:    s_add_u32 s0, s4, s0
; GCN2-NEXT:    s_addc_u32 s1, s5, s1
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v1, s7
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_add_x2 v[2:3], v[0:1]
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %gep = getelementptr i64, ptr %ptr, i64 4
  %tmp0 = atomicrmw volatile add ptr %gep, i64 %in seq_cst
  ret void
}

define amdgpu_kernel void @atomic_add_i64_ret_addr64_offset(ptr %out, ptr %out2, i64 %in, i64 %index) {
; GCN1-LABEL: atomic_add_i64_ret_addr64_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    s_lshl_b64 s[4:5], s[6:7], 3
; GCN1-NEXT:    s_add_u32 s0, s0, s4
; GCN1-NEXT:    s_addc_u32 s1, s1, s5
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_add_x2 v[0:1], v[2:3], v[0:1] glc
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_add_i64_ret_addr64_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    s_lshl_b64 s[4:5], s[6:7], 3
; GCN2-NEXT:    s_add_u32 s0, s0, s4
; GCN2-NEXT:    s_addc_u32 s1, s1, s5
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_add_x2 v[0:1], v[2:3], v[0:1] glc
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %gep = getelementptr i64, ptr %ptr, i64 4
  %tmp0 = atomicrmw volatile add ptr %gep, i64 %in seq_cst
  store i64 %tmp0, ptr %out2
  ret void
}

define amdgpu_kernel void @atomic_add_i64(ptr %out, i64 %in) {
; GCN1-LABEL: atomic_add_i64:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s0
; GCN1-NEXT:    v_mov_b32_e32 v1, s1
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_add_x2 v[0:1], v[2:3]
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_add_i64:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s0
; GCN2-NEXT:    v_mov_b32_e32 v1, s1
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_add_x2 v[0:1], v[2:3]
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    s_endpgm
entry:
  %tmp0 = atomicrmw volatile add ptr %out, i64 %in seq_cst
  ret void
}

define amdgpu_kernel void @atomic_add_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GCN1-LABEL: atomic_add_i64_ret:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN1-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_add_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    v_mov_b32_e32 v2, s6
; GCN1-NEXT:    v_mov_b32_e32 v3, s7
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_add_i64_ret:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
; GCN2-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_add_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    v_mov_b32_e32 v2, s6
; GCN2-NEXT:    v_mov_b32_e32 v3, s7
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %tmp0 = atomicrmw volatile add ptr %out, i64 %in seq_cst
  store i64 %tmp0, ptr %out2
  ret void
}

define amdgpu_kernel void @atomic_add_i64_addr64(ptr %out, i64 %in, i64 %index) {
; GCN1-LABEL: atomic_add_i64_addr64:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN1-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s6
; GCN1-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN1-NEXT:    s_add_u32 s0, s4, s0
; GCN1-NEXT:    s_addc_u32 s1, s5, s1
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v1, s7
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_add_x2 v[2:3], v[0:1]
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_add_i64_addr64:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
; GCN2-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s6
; GCN2-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN2-NEXT:    s_add_u32 s0, s4, s0
; GCN2-NEXT:    s_addc_u32 s1, s5, s1
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v1, s7
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_add_x2 v[2:3], v[0:1]
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %tmp0 = atomicrmw volatile add ptr %ptr, i64 %in seq_cst
  ret void
}

define amdgpu_kernel void @atomic_add_i64_ret_addr64(ptr %out, ptr %out2, i64 %in, i64 %index) {
; GCN1-LABEL: atomic_add_i64_ret_addr64:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    s_lshl_b64 s[4:5], s[6:7], 3
; GCN1-NEXT:    s_add_u32 s0, s0, s4
; GCN1-NEXT:    s_addc_u32 s1, s1, s5
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_add_x2 v[0:1], v[2:3], v[0:1] glc
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_add_i64_ret_addr64:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    s_lshl_b64 s[4:5], s[6:7], 3
; GCN2-NEXT:    s_add_u32 s0, s0, s4
; GCN2-NEXT:    s_addc_u32 s1, s1, s5
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_add_x2 v[0:1], v[2:3], v[0:1] glc
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %tmp0 = atomicrmw volatile add ptr %ptr, i64 %in seq_cst
  store i64 %tmp0, ptr %out2
  ret void
}

define amdgpu_kernel void @atomic_and_i64_offset(ptr %out, i64 %in) {
; GCN1-LABEL: atomic_and_i64_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v0, s2
; GCN1-NEXT:    v_mov_b32_e32 v1, s3
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_and_x2 v[2:3], v[0:1]
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_and_i64_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v0, s2
; GCN2-NEXT:    v_mov_b32_e32 v1, s3
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_and_x2 v[2:3], v[0:1]
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    s_endpgm
entry:
  %gep = getelementptr i64, ptr %out, i64 4
  %tmp0 = atomicrmw volatile and ptr %gep, i64 %in seq_cst
  ret void
}

define amdgpu_kernel void @atomic_and_i64_ret_offset(ptr %out, ptr %out2, i64 %in) {
; GCN1-LABEL: atomic_and_i64_ret_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xd
; GCN1-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_and_x2 v[0:1], v[2:3], v[0:1] glc
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_and_i64_ret_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x34
; GCN2-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_and_x2 v[0:1], v[2:3], v[0:1] glc
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %gep = getelementptr i64, ptr %out, i64 4
  %tmp0 = atomicrmw volatile and ptr %gep, i64 %in seq_cst
  store i64 %tmp0, ptr %out2
  ret void
}

define amdgpu_kernel void @atomic_and_i64_addr64_offset(ptr %out, i64 %in, i64 %index) {
; GCN1-LABEL: atomic_and_i64_addr64_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN1-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s6
; GCN1-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN1-NEXT:    s_add_u32 s0, s4, s0
; GCN1-NEXT:    s_addc_u32 s1, s5, s1
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v1, s7
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_and_x2 v[2:3], v[0:1]
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_and_i64_addr64_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
; GCN2-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s6
; GCN2-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN2-NEXT:    s_add_u32 s0, s4, s0
; GCN2-NEXT:    s_addc_u32 s1, s5, s1
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v1, s7
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_and_x2 v[2:3], v[0:1]
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %gep = getelementptr i64, ptr %ptr, i64 4
  %tmp0 = atomicrmw volatile and ptr %gep, i64 %in seq_cst
  ret void
}

define amdgpu_kernel void @atomic_and_i64_ret_addr64_offset(ptr %out, ptr %out2, i64 %in, i64 %index) {
; GCN1-LABEL: atomic_and_i64_ret_addr64_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    s_lshl_b64 s[4:5], s[6:7], 3
; GCN1-NEXT:    s_add_u32 s0, s0, s4
; GCN1-NEXT:    s_addc_u32 s1, s1, s5
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_and_x2 v[0:1], v[2:3], v[0:1] glc
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_and_i64_ret_addr64_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    s_lshl_b64 s[4:5], s[6:7], 3
; GCN2-NEXT:    s_add_u32 s0, s0, s4
; GCN2-NEXT:    s_addc_u32 s1, s1, s5
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_and_x2 v[0:1], v[2:3], v[0:1] glc
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %gep = getelementptr i64, ptr %ptr, i64 4
  %tmp0 = atomicrmw volatile and ptr %gep, i64 %in seq_cst
  store i64 %tmp0, ptr %out2
  ret void
}

define amdgpu_kernel void @atomic_and_i64(ptr %out, i64 %in) {
; GCN1-LABEL: atomic_and_i64:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s0
; GCN1-NEXT:    v_mov_b32_e32 v1, s1
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_and_x2 v[0:1], v[2:3]
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_and_i64:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s0
; GCN2-NEXT:    v_mov_b32_e32 v1, s1
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_and_x2 v[0:1], v[2:3]
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    s_endpgm
entry:
  %tmp0 = atomicrmw volatile and ptr %out, i64 %in seq_cst
  ret void
}

define amdgpu_kernel void @atomic_and_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GCN1-LABEL: atomic_and_i64_ret:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN1-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_and_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    v_mov_b32_e32 v2, s6
; GCN1-NEXT:    v_mov_b32_e32 v3, s7
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_and_i64_ret:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
; GCN2-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_and_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    v_mov_b32_e32 v2, s6
; GCN2-NEXT:    v_mov_b32_e32 v3, s7
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %tmp0 = atomicrmw volatile and ptr %out, i64 %in seq_cst
  store i64 %tmp0, ptr %out2
  ret void
}

define amdgpu_kernel void @atomic_and_i64_addr64(ptr %out, i64 %in, i64 %index) {
; GCN1-LABEL: atomic_and_i64_addr64:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN1-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s6
; GCN1-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN1-NEXT:    s_add_u32 s0, s4, s0
; GCN1-NEXT:    s_addc_u32 s1, s5, s1
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v1, s7
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_and_x2 v[2:3], v[0:1]
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_and_i64_addr64:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
; GCN2-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s6
; GCN2-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN2-NEXT:    s_add_u32 s0, s4, s0
; GCN2-NEXT:    s_addc_u32 s1, s5, s1
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v1, s7
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_and_x2 v[2:3], v[0:1]
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %tmp0 = atomicrmw volatile and ptr %ptr, i64 %in seq_cst
  ret void
}

define amdgpu_kernel void @atomic_and_i64_ret_addr64(ptr %out, ptr %out2, i64 %in, i64 %index) {
; GCN1-LABEL: atomic_and_i64_ret_addr64:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    s_lshl_b64 s[4:5], s[6:7], 3
; GCN1-NEXT:    s_add_u32 s0, s0, s4
; GCN1-NEXT:    s_addc_u32 s1, s1, s5
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_and_x2 v[0:1], v[2:3], v[0:1] glc
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_and_i64_ret_addr64:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    s_lshl_b64 s[4:5], s[6:7], 3
; GCN2-NEXT:    s_add_u32 s0, s0, s4
; GCN2-NEXT:    s_addc_u32 s1, s1, s5
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_and_x2 v[0:1], v[2:3], v[0:1] glc
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %tmp0 = atomicrmw volatile and ptr %ptr, i64 %in seq_cst
  store i64 %tmp0, ptr %out2
  ret void
}

define amdgpu_kernel void @atomic_sub_i64_offset(ptr %out, i64 %in) {
; GCN1-LABEL: atomic_sub_i64_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v0, s2
; GCN1-NEXT:    v_mov_b32_e32 v1, s3
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_sub_x2 v[2:3], v[0:1]
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_sub_i64_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v0, s2
; GCN2-NEXT:    v_mov_b32_e32 v1, s3
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_sub_x2 v[2:3], v[0:1]
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    s_endpgm
entry:
  %gep = getelementptr i64, ptr %out, i64 4
  %tmp0 = atomicrmw volatile sub ptr %gep, i64 %in seq_cst
  ret void
}

define amdgpu_kernel void @atomic_sub_i64_ret_offset(ptr %out, ptr %out2, i64 %in) {
; GCN1-LABEL: atomic_sub_i64_ret_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xd
; GCN1-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_sub_x2 v[0:1], v[2:3], v[0:1] glc
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_sub_i64_ret_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x34
; GCN2-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_sub_x2 v[0:1], v[2:3], v[0:1] glc
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %gep = getelementptr i64, ptr %out, i64 4
  %tmp0 = atomicrmw volatile sub ptr %gep, i64 %in seq_cst
  store i64 %tmp0, ptr %out2
  ret void
}

define amdgpu_kernel void @atomic_sub_i64_addr64_offset(ptr %out, i64 %in, i64 %index) {
; GCN1-LABEL: atomic_sub_i64_addr64_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN1-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s6
; GCN1-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN1-NEXT:    s_add_u32 s0, s4, s0
; GCN1-NEXT:    s_addc_u32 s1, s5, s1
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v1, s7
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_sub_x2 v[2:3], v[0:1]
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_sub_i64_addr64_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
; GCN2-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s6
; GCN2-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN2-NEXT:    s_add_u32 s0, s4, s0
; GCN2-NEXT:    s_addc_u32 s1, s5, s1
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v1, s7
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_sub_x2 v[2:3], v[0:1]
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %gep = getelementptr i64, ptr %ptr, i64 4
  %tmp0 = atomicrmw volatile sub ptr %gep, i64 %in seq_cst
  ret void
}

define amdgpu_kernel void @atomic_sub_i64_ret_addr64_offset(ptr %out, ptr %out2, i64 %in, i64 %index) {
; GCN1-LABEL: atomic_sub_i64_ret_addr64_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    s_lshl_b64 s[4:5], s[6:7], 3
; GCN1-NEXT:    s_add_u32 s0, s0, s4
; GCN1-NEXT:    s_addc_u32 s1, s1, s5
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_sub_x2 v[0:1], v[2:3], v[0:1] glc
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_sub_i64_ret_addr64_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    s_lshl_b64 s[4:5], s[6:7], 3
; GCN2-NEXT:    s_add_u32 s0, s0, s4
; GCN2-NEXT:    s_addc_u32 s1, s1, s5
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_sub_x2 v[0:1], v[2:3], v[0:1] glc
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %gep = getelementptr i64, ptr %ptr, i64 4
  %tmp0 = atomicrmw volatile sub ptr %gep, i64 %in seq_cst
  store i64 %tmp0, ptr %out2
  ret void
}

define amdgpu_kernel void @atomic_sub_i64(ptr %out, i64 %in) {
; GCN1-LABEL: atomic_sub_i64:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s0
; GCN1-NEXT:    v_mov_b32_e32 v1, s1
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_sub_x2 v[0:1], v[2:3]
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_sub_i64:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s0
; GCN2-NEXT:    v_mov_b32_e32 v1, s1
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_sub_x2 v[0:1], v[2:3]
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    s_endpgm
entry:
  %tmp0 = atomicrmw volatile sub ptr %out, i64 %in seq_cst
  ret void
}

define amdgpu_kernel void @atomic_sub_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GCN1-LABEL: atomic_sub_i64_ret:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN1-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_sub_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    v_mov_b32_e32 v2, s6
; GCN1-NEXT:    v_mov_b32_e32 v3, s7
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_sub_i64_ret:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
; GCN2-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_sub_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    v_mov_b32_e32 v2, s6
; GCN2-NEXT:    v_mov_b32_e32 v3, s7
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %tmp0 = atomicrmw volatile sub ptr %out, i64 %in seq_cst
  store i64 %tmp0, ptr %out2
  ret void
}

define amdgpu_kernel void @atomic_sub_i64_addr64(ptr %out, i64 %in, i64 %index) {
; GCN1-LABEL: atomic_sub_i64_addr64:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN1-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s6
; GCN1-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN1-NEXT:    s_add_u32 s0, s4, s0
; GCN1-NEXT:    s_addc_u32 s1, s5, s1
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v1, s7
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_sub_x2 v[2:3], v[0:1]
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_sub_i64_addr64:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
; GCN2-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s6
; GCN2-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN2-NEXT:    s_add_u32 s0, s4, s0
; GCN2-NEXT:    s_addc_u32 s1, s5, s1
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v1, s7
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_sub_x2 v[2:3], v[0:1]
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %tmp0 = atomicrmw volatile sub ptr %ptr, i64 %in seq_cst
  ret void
}

define amdgpu_kernel void @atomic_sub_i64_ret_addr64(ptr %out, ptr %out2, i64 %in, i64 %index) {
; GCN1-LABEL: atomic_sub_i64_ret_addr64:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    s_lshl_b64 s[4:5], s[6:7], 3
; GCN1-NEXT:    s_add_u32 s0, s0, s4
; GCN1-NEXT:    s_addc_u32 s1, s1, s5
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_sub_x2 v[0:1], v[2:3], v[0:1] glc
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_sub_i64_ret_addr64:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    s_lshl_b64 s[4:5], s[6:7], 3
; GCN2-NEXT:    s_add_u32 s0, s0, s4
; GCN2-NEXT:    s_addc_u32 s1, s1, s5
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_sub_x2 v[0:1], v[2:3], v[0:1] glc
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %tmp0 = atomicrmw volatile sub ptr %ptr, i64 %in seq_cst
  store i64 %tmp0, ptr %out2
  ret void
}

define amdgpu_kernel void @atomic_max_i64_offset(ptr %out, i64 %in) {
; GCN1-LABEL: atomic_max_i64_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v0, s2
; GCN1-NEXT:    v_mov_b32_e32 v1, s3
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_smax_x2 v[2:3], v[0:1]
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_max_i64_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v0, s2
; GCN2-NEXT:    v_mov_b32_e32 v1, s3
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_smax_x2 v[2:3], v[0:1]
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    s_endpgm
entry:
  %gep = getelementptr i64, ptr %out, i64 4
  %tmp0 = atomicrmw volatile max ptr %gep, i64 %in syncscope("workgroup") seq_cst
  ret void
}

define amdgpu_kernel void @atomic_max_i64_ret_offset(ptr %out, ptr %out2, i64 %in) {
; GCN1-LABEL: atomic_max_i64_ret_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xd
; GCN1-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_smax_x2 v[0:1], v[2:3], v[0:1] glc
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    s_waitcnt vmcnt(0)
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_max_i64_ret_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x34
; GCN2-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_smax_x2 v[0:1], v[2:3], v[0:1] glc
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    s_waitcnt vmcnt(0)
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %gep = getelementptr i64, ptr %out, i64 4
  %tmp0 = atomicrmw volatile max ptr %gep, i64 %in syncscope("workgroup") seq_cst
  store i64 %tmp0, ptr %out2
  ret void
}

define amdgpu_kernel void @atomic_max_i64_addr64_offset(ptr %out, i64 %in, i64 %index) {
; GCN1-LABEL: atomic_max_i64_addr64_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN1-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s6
; GCN1-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN1-NEXT:    s_add_u32 s0, s4, s0
; GCN1-NEXT:    s_addc_u32 s1, s5, s1
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v1, s7
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_smax_x2 v[2:3], v[0:1]
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_max_i64_addr64_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
; GCN2-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s6
; GCN2-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN2-NEXT:    s_add_u32 s0, s4, s0
; GCN2-NEXT:    s_addc_u32 s1, s5, s1
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v1, s7
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_smax_x2 v[2:3], v[0:1]
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %gep = getelementptr i64, ptr %ptr, i64 4
  %tmp0 = atomicrmw volatile max ptr %gep, i64 %in syncscope("workgroup") seq_cst
  ret void
}

define amdgpu_kernel void @atomic_max_i64_ret_addr64_offset(ptr %out, ptr %out2, i64 %in, i64 %index) {
; GCN1-LABEL: atomic_max_i64_ret_addr64_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    s_lshl_b64 s[4:5], s[6:7], 3
; GCN1-NEXT:    s_add_u32 s0, s0, s4
; GCN1-NEXT:    s_addc_u32 s1, s1, s5
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_smax_x2 v[0:1], v[2:3], v[0:1] glc
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    s_waitcnt vmcnt(0)
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_max_i64_ret_addr64_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    s_lshl_b64 s[4:5], s[6:7], 3
; GCN2-NEXT:    s_add_u32 s0, s0, s4
; GCN2-NEXT:    s_addc_u32 s1, s1, s5
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_smax_x2 v[0:1], v[2:3], v[0:1] glc
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    s_waitcnt vmcnt(0)
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %gep = getelementptr i64, ptr %ptr, i64 4
  %tmp0 = atomicrmw volatile max ptr %gep, i64 %in syncscope("workgroup") seq_cst
  store i64 %tmp0, ptr %out2
  ret void
}

define amdgpu_kernel void @atomic_max_i64(ptr %out, i64 %in) {
; GCN1-LABEL: atomic_max_i64:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s0
; GCN1-NEXT:    v_mov_b32_e32 v1, s1
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_smax_x2 v[0:1], v[2:3]
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_max_i64:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s0
; GCN2-NEXT:    v_mov_b32_e32 v1, s1
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_smax_x2 v[0:1], v[2:3]
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    s_endpgm
entry:
  %tmp0 = atomicrmw volatile max ptr %out, i64 %in syncscope("workgroup") seq_cst
  ret void
}

define amdgpu_kernel void @atomic_max_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GCN1-LABEL: atomic_max_i64_ret:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN1-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_smax_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v2, s6
; GCN1-NEXT:    v_mov_b32_e32 v3, s7
; GCN1-NEXT:    s_waitcnt vmcnt(0)
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_max_i64_ret:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
; GCN2-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_smax_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v2, s6
; GCN2-NEXT:    v_mov_b32_e32 v3, s7
; GCN2-NEXT:    s_waitcnt vmcnt(0)
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %tmp0 = atomicrmw volatile max ptr %out, i64 %in syncscope("workgroup") seq_cst
  store i64 %tmp0, ptr %out2
  ret void
}

define amdgpu_kernel void @atomic_max_i64_addr64(ptr %out, i64 %in, i64 %index) {
; GCN1-LABEL: atomic_max_i64_addr64:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN1-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s6
; GCN1-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN1-NEXT:    s_add_u32 s0, s4, s0
; GCN1-NEXT:    s_addc_u32 s1, s5, s1
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v1, s7
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_smax_x2 v[2:3], v[0:1]
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_max_i64_addr64:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
; GCN2-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s6
; GCN2-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN2-NEXT:    s_add_u32 s0, s4, s0
; GCN2-NEXT:    s_addc_u32 s1, s5, s1
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v1, s7
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_smax_x2 v[2:3], v[0:1]
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %tmp0 = atomicrmw volatile max ptr %ptr, i64 %in syncscope("workgroup") seq_cst
  ret void
}

define amdgpu_kernel void @atomic_max_i64_ret_addr64(ptr %out, ptr %out2, i64 %in, i64 %index) {
; GCN1-LABEL: atomic_max_i64_ret_addr64:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    s_lshl_b64 s[4:5], s[6:7], 3
; GCN1-NEXT:    s_add_u32 s0, s0, s4
; GCN1-NEXT:    s_addc_u32 s1, s1, s5
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_smax_x2 v[0:1], v[2:3], v[0:1] glc
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    s_waitcnt vmcnt(0)
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_max_i64_ret_addr64:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    s_lshl_b64 s[4:5], s[6:7], 3
; GCN2-NEXT:    s_add_u32 s0, s0, s4
; GCN2-NEXT:    s_addc_u32 s1, s1, s5
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_smax_x2 v[0:1], v[2:3], v[0:1] glc
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    s_waitcnt vmcnt(0)
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %tmp0 = atomicrmw volatile max ptr %ptr, i64 %in syncscope("workgroup") seq_cst
  store i64 %tmp0, ptr %out2
  ret void
}

define amdgpu_kernel void @atomic_umax_i64_offset(ptr %out, i64 %in) {
; GCN1-LABEL: atomic_umax_i64_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v0, s2
; GCN1-NEXT:    v_mov_b32_e32 v1, s3
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_umax_x2 v[2:3], v[0:1]
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_umax_i64_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v0, s2
; GCN2-NEXT:    v_mov_b32_e32 v1, s3
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_umax_x2 v[2:3], v[0:1]
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    s_endpgm
entry:
  %gep = getelementptr i64, ptr %out, i64 4
  %tmp0 = atomicrmw volatile umax ptr %gep, i64 %in syncscope("workgroup") seq_cst
  ret void
}

define amdgpu_kernel void @atomic_umax_i64_ret_offset(ptr %out, ptr %out2, i64 %in) {
; GCN1-LABEL: atomic_umax_i64_ret_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xd
; GCN1-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_umax_x2 v[0:1], v[2:3], v[0:1] glc
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    s_waitcnt vmcnt(0)
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_umax_i64_ret_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x34
; GCN2-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_umax_x2 v[0:1], v[2:3], v[0:1] glc
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    s_waitcnt vmcnt(0)
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %gep = getelementptr i64, ptr %out, i64 4
  %tmp0 = atomicrmw volatile umax ptr %gep, i64 %in syncscope("workgroup") seq_cst
  store i64 %tmp0, ptr %out2
  ret void
}

define amdgpu_kernel void @atomic_umax_i64_addr64_offset(ptr %out, i64 %in, i64 %index) {
; GCN1-LABEL: atomic_umax_i64_addr64_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN1-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s6
; GCN1-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN1-NEXT:    s_add_u32 s0, s4, s0
; GCN1-NEXT:    s_addc_u32 s1, s5, s1
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v1, s7
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_umax_x2 v[2:3], v[0:1]
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_umax_i64_addr64_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
; GCN2-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s6
; GCN2-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN2-NEXT:    s_add_u32 s0, s4, s0
; GCN2-NEXT:    s_addc_u32 s1, s5, s1
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v1, s7
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_umax_x2 v[2:3], v[0:1]
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %gep = getelementptr i64, ptr %ptr, i64 4
  %tmp0 = atomicrmw volatile umax ptr %gep, i64 %in syncscope("workgroup") seq_cst
  ret void
}

define amdgpu_kernel void @atomic_umax_i64_ret_addr64_offset(ptr %out, ptr %out2, i64 %in, i64 %index) {
; GCN1-LABEL: atomic_umax_i64_ret_addr64_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    s_lshl_b64 s[4:5], s[6:7], 3
; GCN1-NEXT:    s_add_u32 s0, s0, s4
; GCN1-NEXT:    s_addc_u32 s1, s1, s5
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_umax_x2 v[0:1], v[2:3], v[0:1] glc
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    s_waitcnt vmcnt(0)
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_umax_i64_ret_addr64_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    s_lshl_b64 s[4:5], s[6:7], 3
; GCN2-NEXT:    s_add_u32 s0, s0, s4
; GCN2-NEXT:    s_addc_u32 s1, s1, s5
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_umax_x2 v[0:1], v[2:3], v[0:1] glc
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    s_waitcnt vmcnt(0)
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %gep = getelementptr i64, ptr %ptr, i64 4
  %tmp0 = atomicrmw volatile umax ptr %gep, i64 %in syncscope("workgroup") seq_cst
  store i64 %tmp0, ptr %out2
  ret void
}

define amdgpu_kernel void @atomic_umax_i64(ptr %out, i64 %in) {
; GCN1-LABEL: atomic_umax_i64:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s0
; GCN1-NEXT:    v_mov_b32_e32 v1, s1
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_umax_x2 v[0:1], v[2:3]
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_umax_i64:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s0
; GCN2-NEXT:    v_mov_b32_e32 v1, s1
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_umax_x2 v[0:1], v[2:3]
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    s_endpgm
entry:
  %tmp0 = atomicrmw volatile umax ptr %out, i64 %in syncscope("workgroup") seq_cst
  ret void
}

define amdgpu_kernel void @atomic_umax_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GCN1-LABEL: atomic_umax_i64_ret:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN1-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_umax_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v2, s6
; GCN1-NEXT:    v_mov_b32_e32 v3, s7
; GCN1-NEXT:    s_waitcnt vmcnt(0)
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_umax_i64_ret:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
; GCN2-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_umax_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v2, s6
; GCN2-NEXT:    v_mov_b32_e32 v3, s7
; GCN2-NEXT:    s_waitcnt vmcnt(0)
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %tmp0 = atomicrmw volatile umax ptr %out, i64 %in syncscope("workgroup") seq_cst
  store i64 %tmp0, ptr %out2
  ret void
}

define amdgpu_kernel void @atomic_umax_i64_addr64(ptr %out, i64 %in, i64 %index) {
; GCN1-LABEL: atomic_umax_i64_addr64:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN1-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s6
; GCN1-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN1-NEXT:    s_add_u32 s0, s4, s0
; GCN1-NEXT:    s_addc_u32 s1, s5, s1
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v1, s7
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_umax_x2 v[2:3], v[0:1]
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_umax_i64_addr64:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
; GCN2-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s6
; GCN2-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN2-NEXT:    s_add_u32 s0, s4, s0
; GCN2-NEXT:    s_addc_u32 s1, s5, s1
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v1, s7
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_umax_x2 v[2:3], v[0:1]
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %tmp0 = atomicrmw volatile umax ptr %ptr, i64 %in syncscope("workgroup") seq_cst
  ret void
}

define amdgpu_kernel void @atomic_umax_i64_ret_addr64(ptr %out, ptr %out2, i64 %in, i64 %index) {
; GCN1-LABEL: atomic_umax_i64_ret_addr64:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    s_lshl_b64 s[4:5], s[6:7], 3
; GCN1-NEXT:    s_add_u32 s0, s0, s4
; GCN1-NEXT:    s_addc_u32 s1, s1, s5
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_umax_x2 v[0:1], v[2:3], v[0:1] glc
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    s_waitcnt vmcnt(0)
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_umax_i64_ret_addr64:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    s_lshl_b64 s[4:5], s[6:7], 3
; GCN2-NEXT:    s_add_u32 s0, s0, s4
; GCN2-NEXT:    s_addc_u32 s1, s1, s5
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_umax_x2 v[0:1], v[2:3], v[0:1] glc
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    s_waitcnt vmcnt(0)
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %tmp0 = atomicrmw volatile umax ptr %ptr, i64 %in syncscope("workgroup") seq_cst
  store i64 %tmp0, ptr %out2
  ret void
}

define amdgpu_kernel void @atomic_min_i64_offset(ptr %out, i64 %in) {
; GCN1-LABEL: atomic_min_i64_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v0, s2
; GCN1-NEXT:    v_mov_b32_e32 v1, s3
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_smin_x2 v[2:3], v[0:1]
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_min_i64_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v0, s2
; GCN2-NEXT:    v_mov_b32_e32 v1, s3
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_smin_x2 v[2:3], v[0:1]
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    s_endpgm
entry:
  %gep = getelementptr i64, ptr %out, i64 4
  %tmp0 = atomicrmw volatile min ptr %gep, i64 %in syncscope("workgroup") seq_cst
  ret void
}

define amdgpu_kernel void @atomic_min_i64_ret_offset(ptr %out, ptr %out2, i64 %in) {
; GCN1-LABEL: atomic_min_i64_ret_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xd
; GCN1-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_smin_x2 v[0:1], v[2:3], v[0:1] glc
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    s_waitcnt vmcnt(0)
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_min_i64_ret_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x34
; GCN2-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_smin_x2 v[0:1], v[2:3], v[0:1] glc
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    s_waitcnt vmcnt(0)
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %gep = getelementptr i64, ptr %out, i64 4
  %tmp0 = atomicrmw volatile min ptr %gep, i64 %in syncscope("workgroup") seq_cst
  store i64 %tmp0, ptr %out2
  ret void
}

define amdgpu_kernel void @atomic_min_i64_addr64_offset(ptr %out, i64 %in, i64 %index) {
; GCN1-LABEL: atomic_min_i64_addr64_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN1-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s6
; GCN1-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN1-NEXT:    s_add_u32 s0, s4, s0
; GCN1-NEXT:    s_addc_u32 s1, s5, s1
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v1, s7
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_smin_x2 v[2:3], v[0:1]
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_min_i64_addr64_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
; GCN2-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s6
; GCN2-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN2-NEXT:    s_add_u32 s0, s4, s0
; GCN2-NEXT:    s_addc_u32 s1, s5, s1
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v1, s7
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_smin_x2 v[2:3], v[0:1]
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %gep = getelementptr i64, ptr %ptr, i64 4
  %tmp0 = atomicrmw volatile min ptr %gep, i64 %in syncscope("workgroup") seq_cst
  ret void
}

define amdgpu_kernel void @atomic_min_i64_ret_addr64_offset(ptr %out, ptr %out2, i64 %in, i64 %index) {
; GCN1-LABEL: atomic_min_i64_ret_addr64_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    s_lshl_b64 s[4:5], s[6:7], 3
; GCN1-NEXT:    s_add_u32 s0, s0, s4
; GCN1-NEXT:    s_addc_u32 s1, s1, s5
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_smin_x2 v[0:1], v[2:3], v[0:1] glc
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    s_waitcnt vmcnt(0)
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_min_i64_ret_addr64_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    s_lshl_b64 s[4:5], s[6:7], 3
; GCN2-NEXT:    s_add_u32 s0, s0, s4
; GCN2-NEXT:    s_addc_u32 s1, s1, s5
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_smin_x2 v[0:1], v[2:3], v[0:1] glc
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    s_waitcnt vmcnt(0)
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %gep = getelementptr i64, ptr %ptr, i64 4
  %tmp0 = atomicrmw volatile min ptr %gep, i64 %in syncscope("workgroup") seq_cst
  store i64 %tmp0, ptr %out2
  ret void
}

define amdgpu_kernel void @atomic_min_i64(ptr %out, i64 %in) {
; GCN1-LABEL: atomic_min_i64:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s0
; GCN1-NEXT:    v_mov_b32_e32 v1, s1
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_smin_x2 v[0:1], v[2:3]
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_min_i64:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s0
; GCN2-NEXT:    v_mov_b32_e32 v1, s1
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_smin_x2 v[0:1], v[2:3]
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    s_endpgm
entry:
  %tmp0 = atomicrmw volatile min ptr %out, i64 %in syncscope("workgroup") seq_cst
  ret void
}

define amdgpu_kernel void @atomic_min_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GCN1-LABEL: atomic_min_i64_ret:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN1-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_smin_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v2, s6
; GCN1-NEXT:    v_mov_b32_e32 v3, s7
; GCN1-NEXT:    s_waitcnt vmcnt(0)
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_min_i64_ret:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
; GCN2-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_smin_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v2, s6
; GCN2-NEXT:    v_mov_b32_e32 v3, s7
; GCN2-NEXT:    s_waitcnt vmcnt(0)
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %tmp0 = atomicrmw volatile min ptr %out, i64 %in syncscope("workgroup") seq_cst
  store i64 %tmp0, ptr %out2
  ret void
}

define amdgpu_kernel void @atomic_min_i64_addr64(ptr %out, i64 %in, i64 %index) {
; GCN1-LABEL: atomic_min_i64_addr64:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN1-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s6
; GCN1-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN1-NEXT:    s_add_u32 s0, s4, s0
; GCN1-NEXT:    s_addc_u32 s1, s5, s1
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v1, s7
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_smin_x2 v[2:3], v[0:1]
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_min_i64_addr64:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
; GCN2-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s6
; GCN2-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN2-NEXT:    s_add_u32 s0, s4, s0
; GCN2-NEXT:    s_addc_u32 s1, s5, s1
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v1, s7
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_smin_x2 v[2:3], v[0:1]
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %tmp0 = atomicrmw volatile min ptr %ptr, i64 %in syncscope("workgroup") seq_cst
  ret void
}

define amdgpu_kernel void @atomic_min_i64_ret_addr64(ptr %out, ptr %out2, i64 %in, i64 %index) {
; GCN1-LABEL: atomic_min_i64_ret_addr64:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    s_lshl_b64 s[4:5], s[6:7], 3
; GCN1-NEXT:    s_add_u32 s0, s0, s4
; GCN1-NEXT:    s_addc_u32 s1, s1, s5
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_smin_x2 v[0:1], v[2:3], v[0:1] glc
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    s_waitcnt vmcnt(0)
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_min_i64_ret_addr64:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    s_lshl_b64 s[4:5], s[6:7], 3
; GCN2-NEXT:    s_add_u32 s0, s0, s4
; GCN2-NEXT:    s_addc_u32 s1, s1, s5
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_smin_x2 v[0:1], v[2:3], v[0:1] glc
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    s_waitcnt vmcnt(0)
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %tmp0 = atomicrmw volatile min ptr %ptr, i64 %in syncscope("workgroup") seq_cst
  store i64 %tmp0, ptr %out2
  ret void
}

define amdgpu_kernel void @atomic_umin_i64_offset(ptr %out, i64 %in) {
; GCN1-LABEL: atomic_umin_i64_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v0, s2
; GCN1-NEXT:    v_mov_b32_e32 v1, s3
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_umin_x2 v[2:3], v[0:1]
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_umin_i64_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v0, s2
; GCN2-NEXT:    v_mov_b32_e32 v1, s3
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_umin_x2 v[2:3], v[0:1]
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    s_endpgm
entry:
  %gep = getelementptr i64, ptr %out, i64 4
  %tmp0 = atomicrmw volatile umin ptr %gep, i64 %in syncscope("workgroup") seq_cst
  ret void
}

define amdgpu_kernel void @atomic_umin_i64_ret_offset(ptr %out, ptr %out2, i64 %in) {
; GCN1-LABEL: atomic_umin_i64_ret_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xd
; GCN1-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_umin_x2 v[0:1], v[2:3], v[0:1] glc
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    s_waitcnt vmcnt(0)
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_umin_i64_ret_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x34
; GCN2-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_umin_x2 v[0:1], v[2:3], v[0:1] glc
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    s_waitcnt vmcnt(0)
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %gep = getelementptr i64, ptr %out, i64 4
  %tmp0 = atomicrmw volatile umin ptr %gep, i64 %in syncscope("workgroup") seq_cst
  store i64 %tmp0, ptr %out2
  ret void
}

define amdgpu_kernel void @atomic_umin_i64_addr64_offset(ptr %out, i64 %in, i64 %index) {
; GCN1-LABEL: atomic_umin_i64_addr64_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN1-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s6
; GCN1-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN1-NEXT:    s_add_u32 s0, s4, s0
; GCN1-NEXT:    s_addc_u32 s1, s5, s1
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v1, s7
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_umin_x2 v[2:3], v[0:1]
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_umin_i64_addr64_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
; GCN2-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s6
; GCN2-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN2-NEXT:    s_add_u32 s0, s4, s0
; GCN2-NEXT:    s_addc_u32 s1, s5, s1
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v1, s7
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_umin_x2 v[2:3], v[0:1]
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %gep = getelementptr i64, ptr %ptr, i64 4
  %tmp0 = atomicrmw volatile umin ptr %gep, i64 %in syncscope("workgroup") seq_cst
  ret void
}

define amdgpu_kernel void @atomic_umin_i64_ret_addr64_offset(ptr %out, ptr %out2, i64 %in, i64 %index) {
; GCN1-LABEL: atomic_umin_i64_ret_addr64_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    s_lshl_b64 s[4:5], s[6:7], 3
; GCN1-NEXT:    s_add_u32 s0, s0, s4
; GCN1-NEXT:    s_addc_u32 s1, s1, s5
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_umin_x2 v[0:1], v[2:3], v[0:1] glc
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    s_waitcnt vmcnt(0)
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_umin_i64_ret_addr64_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    s_lshl_b64 s[4:5], s[6:7], 3
; GCN2-NEXT:    s_add_u32 s0, s0, s4
; GCN2-NEXT:    s_addc_u32 s1, s1, s5
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_umin_x2 v[0:1], v[2:3], v[0:1] glc
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    s_waitcnt vmcnt(0)
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %gep = getelementptr i64, ptr %ptr, i64 4
  %tmp0 = atomicrmw volatile umin ptr %gep, i64 %in syncscope("workgroup") seq_cst
  store i64 %tmp0, ptr %out2
  ret void
}

define amdgpu_kernel void @atomic_umin_i64(ptr %out, i64 %in) {
; GCN1-LABEL: atomic_umin_i64:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s0
; GCN1-NEXT:    v_mov_b32_e32 v1, s1
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_umin_x2 v[0:1], v[2:3]
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_umin_i64:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s0
; GCN2-NEXT:    v_mov_b32_e32 v1, s1
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_umin_x2 v[0:1], v[2:3]
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    s_endpgm
entry:
  %tmp0 = atomicrmw volatile umin ptr %out, i64 %in syncscope("workgroup") seq_cst
  ret void
}

define amdgpu_kernel void @atomic_umin_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GCN1-LABEL: atomic_umin_i64_ret:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN1-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_umin_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v2, s6
; GCN1-NEXT:    v_mov_b32_e32 v3, s7
; GCN1-NEXT:    s_waitcnt vmcnt(0)
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_umin_i64_ret:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
; GCN2-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_umin_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v2, s6
; GCN2-NEXT:    v_mov_b32_e32 v3, s7
; GCN2-NEXT:    s_waitcnt vmcnt(0)
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %tmp0 = atomicrmw volatile umin ptr %out, i64 %in syncscope("workgroup") seq_cst
  store i64 %tmp0, ptr %out2
  ret void
}

define amdgpu_kernel void @atomic_umin_i64_addr64(ptr %out, i64 %in, i64 %index) {
; GCN1-LABEL: atomic_umin_i64_addr64:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN1-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s6
; GCN1-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN1-NEXT:    s_add_u32 s0, s4, s0
; GCN1-NEXT:    s_addc_u32 s1, s5, s1
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v1, s7
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_umin_x2 v[2:3], v[0:1]
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_umin_i64_addr64:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
; GCN2-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s6
; GCN2-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN2-NEXT:    s_add_u32 s0, s4, s0
; GCN2-NEXT:    s_addc_u32 s1, s5, s1
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v1, s7
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_umin_x2 v[2:3], v[0:1]
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %tmp0 = atomicrmw volatile umin ptr %ptr, i64 %in syncscope("workgroup") seq_cst
  ret void
}

define amdgpu_kernel void @atomic_umin_i64_ret_addr64(ptr %out, ptr %out2, i64 %in, i64 %index) {
; GCN1-LABEL: atomic_umin_i64_ret_addr64:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    s_lshl_b64 s[4:5], s[6:7], 3
; GCN1-NEXT:    s_add_u32 s0, s0, s4
; GCN1-NEXT:    s_addc_u32 s1, s1, s5
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_umin_x2 v[0:1], v[2:3], v[0:1] glc
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    s_waitcnt vmcnt(0)
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_umin_i64_ret_addr64:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    s_lshl_b64 s[4:5], s[6:7], 3
; GCN2-NEXT:    s_add_u32 s0, s0, s4
; GCN2-NEXT:    s_addc_u32 s1, s1, s5
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_umin_x2 v[0:1], v[2:3], v[0:1] glc
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    s_waitcnt vmcnt(0)
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %tmp0 = atomicrmw volatile umin ptr %ptr, i64 %in syncscope("workgroup") seq_cst
  store i64 %tmp0, ptr %out2
  ret void
}

define amdgpu_kernel void @atomic_or_i64_offset(ptr %out, i64 %in) {
; GCN1-LABEL: atomic_or_i64_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v0, s2
; GCN1-NEXT:    v_mov_b32_e32 v1, s3
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_or_x2 v[2:3], v[0:1]
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_or_i64_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v0, s2
; GCN2-NEXT:    v_mov_b32_e32 v1, s3
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_or_x2 v[2:3], v[0:1]
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    s_endpgm
entry:
  %gep = getelementptr i64, ptr %out, i64 4
  %tmp0 = atomicrmw volatile or ptr %gep, i64 %in seq_cst
  ret void
}

define amdgpu_kernel void @atomic_or_i64_ret_offset(ptr %out, ptr %out2, i64 %in) {
; GCN1-LABEL: atomic_or_i64_ret_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xd
; GCN1-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_or_x2 v[0:1], v[2:3], v[0:1] glc
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_or_i64_ret_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x34
; GCN2-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_or_x2 v[0:1], v[2:3], v[0:1] glc
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %gep = getelementptr i64, ptr %out, i64 4
  %tmp0 = atomicrmw volatile or ptr %gep, i64 %in seq_cst
  store i64 %tmp0, ptr %out2
  ret void
}

define amdgpu_kernel void @atomic_or_i64_addr64_offset(ptr %out, i64 %in, i64 %index) {
; GCN1-LABEL: atomic_or_i64_addr64_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN1-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s6
; GCN1-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN1-NEXT:    s_add_u32 s0, s4, s0
; GCN1-NEXT:    s_addc_u32 s1, s5, s1
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v1, s7
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_or_x2 v[2:3], v[0:1]
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_or_i64_addr64_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
; GCN2-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s6
; GCN2-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN2-NEXT:    s_add_u32 s0, s4, s0
; GCN2-NEXT:    s_addc_u32 s1, s5, s1
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v1, s7
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_or_x2 v[2:3], v[0:1]
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %gep = getelementptr i64, ptr %ptr, i64 4
  %tmp0 = atomicrmw volatile or ptr %gep, i64 %in seq_cst
  ret void
}

define amdgpu_kernel void @atomic_or_i64_ret_addr64_offset(ptr %out, ptr %out2, i64 %in, i64 %index) {
; GCN1-LABEL: atomic_or_i64_ret_addr64_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    s_lshl_b64 s[4:5], s[6:7], 3
; GCN1-NEXT:    s_add_u32 s0, s0, s4
; GCN1-NEXT:    s_addc_u32 s1, s1, s5
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_or_x2 v[0:1], v[2:3], v[0:1] glc
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_or_i64_ret_addr64_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    s_lshl_b64 s[4:5], s[6:7], 3
; GCN2-NEXT:    s_add_u32 s0, s0, s4
; GCN2-NEXT:    s_addc_u32 s1, s1, s5
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_or_x2 v[0:1], v[2:3], v[0:1] glc
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %gep = getelementptr i64, ptr %ptr, i64 4
  %tmp0 = atomicrmw volatile or ptr %gep, i64 %in seq_cst
  store i64 %tmp0, ptr %out2
  ret void
}

define amdgpu_kernel void @atomic_or_i64(ptr %out, i64 %in) {
; GCN1-LABEL: atomic_or_i64:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s0
; GCN1-NEXT:    v_mov_b32_e32 v1, s1
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_or_x2 v[0:1], v[2:3]
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_or_i64:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s0
; GCN2-NEXT:    v_mov_b32_e32 v1, s1
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_or_x2 v[0:1], v[2:3]
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    s_endpgm
entry:
  %tmp0 = atomicrmw volatile or ptr %out, i64 %in seq_cst
  ret void
}

define amdgpu_kernel void @atomic_or_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GCN1-LABEL: atomic_or_i64_ret:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN1-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_or_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    v_mov_b32_e32 v2, s6
; GCN1-NEXT:    v_mov_b32_e32 v3, s7
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_or_i64_ret:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
; GCN2-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_or_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    v_mov_b32_e32 v2, s6
; GCN2-NEXT:    v_mov_b32_e32 v3, s7
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %tmp0 = atomicrmw volatile or ptr %out, i64 %in seq_cst
  store i64 %tmp0, ptr %out2
  ret void
}

define amdgpu_kernel void @atomic_or_i64_addr64(ptr %out, i64 %in, i64 %index) {
; GCN1-LABEL: atomic_or_i64_addr64:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN1-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s6
; GCN1-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN1-NEXT:    s_add_u32 s0, s4, s0
; GCN1-NEXT:    s_addc_u32 s1, s5, s1
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v1, s7
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_or_x2 v[2:3], v[0:1]
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_or_i64_addr64:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
; GCN2-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s6
; GCN2-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN2-NEXT:    s_add_u32 s0, s4, s0
; GCN2-NEXT:    s_addc_u32 s1, s5, s1
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v1, s7
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_or_x2 v[2:3], v[0:1]
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %tmp0 = atomicrmw volatile or ptr %ptr, i64 %in seq_cst
  ret void
}

define amdgpu_kernel void @atomic_or_i64_ret_addr64(ptr %out, ptr %out2, i64 %in, i64 %index) {
; GCN1-LABEL: atomic_or_i64_ret_addr64:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    s_lshl_b64 s[4:5], s[6:7], 3
; GCN1-NEXT:    s_add_u32 s0, s0, s4
; GCN1-NEXT:    s_addc_u32 s1, s1, s5
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_or_x2 v[0:1], v[2:3], v[0:1] glc
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_or_i64_ret_addr64:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    s_lshl_b64 s[4:5], s[6:7], 3
; GCN2-NEXT:    s_add_u32 s0, s0, s4
; GCN2-NEXT:    s_addc_u32 s1, s1, s5
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_or_x2 v[0:1], v[2:3], v[0:1] glc
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %tmp0 = atomicrmw volatile or ptr %ptr, i64 %in seq_cst
  store i64 %tmp0, ptr %out2
  ret void
}

define amdgpu_kernel void @atomic_xchg_i64_offset(ptr %out, i64 %in) {
; GCN1-LABEL: atomic_xchg_i64_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v0, s2
; GCN1-NEXT:    v_mov_b32_e32 v1, s3
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_swap_x2 v[2:3], v[0:1]
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_xchg_i64_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v0, s2
; GCN2-NEXT:    v_mov_b32_e32 v1, s3
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_swap_x2 v[2:3], v[0:1]
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    s_endpgm
entry:
  %gep = getelementptr i64, ptr %out, i64 4
  %tmp0 = atomicrmw volatile xchg ptr %gep, i64 %in seq_cst
  ret void
}

define amdgpu_kernel void @atomic_xchg_f64_offset(ptr %out, double %in) {
; GCN1-LABEL: atomic_xchg_f64_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v0, s2
; GCN1-NEXT:    v_mov_b32_e32 v1, s3
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_swap_x2 v[2:3], v[0:1]
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_xchg_f64_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v0, s2
; GCN2-NEXT:    v_mov_b32_e32 v1, s3
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_swap_x2 v[2:3], v[0:1]
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    s_endpgm
entry:
  %gep = getelementptr double, ptr %out, i64 4
  %tmp0 = atomicrmw volatile xchg ptr %gep, double %in seq_cst
  ret void
}

define amdgpu_kernel void @atomic_xchg_pointer_offset(ptr %out, ptr %in) {
; GCN1-LABEL: atomic_xchg_pointer_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v0, s2
; GCN1-NEXT:    v_mov_b32_e32 v1, s3
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_swap_x2 v[2:3], v[0:1]
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_xchg_pointer_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v0, s2
; GCN2-NEXT:    v_mov_b32_e32 v1, s3
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_swap_x2 v[2:3], v[0:1]
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    s_endpgm
entry:
  %gep = getelementptr ptr, ptr %out, i32 4
  %val = atomicrmw volatile xchg ptr %gep, ptr %in seq_cst
  ret void
}

define amdgpu_kernel void @atomic_xchg_i64_ret_offset(ptr %out, ptr %out2, i64 %in) {
; GCN1-LABEL: atomic_xchg_i64_ret_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xd
; GCN1-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_swap_x2 v[0:1], v[2:3], v[0:1] glc
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_xchg_i64_ret_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x34
; GCN2-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_swap_x2 v[0:1], v[2:3], v[0:1] glc
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %gep = getelementptr i64, ptr %out, i64 4
  %tmp0 = atomicrmw volatile xchg ptr %gep, i64 %in seq_cst
  store i64 %tmp0, ptr %out2
  ret void
}

define amdgpu_kernel void @atomic_xchg_i64_addr64_offset(ptr %out, i64 %in, i64 %index) {
; GCN1-LABEL: atomic_xchg_i64_addr64_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN1-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s6
; GCN1-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN1-NEXT:    s_add_u32 s0, s4, s0
; GCN1-NEXT:    s_addc_u32 s1, s5, s1
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v1, s7
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_swap_x2 v[2:3], v[0:1]
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_xchg_i64_addr64_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
; GCN2-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s6
; GCN2-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN2-NEXT:    s_add_u32 s0, s4, s0
; GCN2-NEXT:    s_addc_u32 s1, s5, s1
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v1, s7
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_swap_x2 v[2:3], v[0:1]
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %gep = getelementptr i64, ptr %ptr, i64 4
  %tmp0 = atomicrmw volatile xchg ptr %gep, i64 %in seq_cst
  ret void
}

define amdgpu_kernel void @atomic_xchg_i64_ret_addr64_offset(ptr %out, ptr %out2, i64 %in, i64 %index) {
; GCN1-LABEL: atomic_xchg_i64_ret_addr64_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    s_lshl_b64 s[4:5], s[6:7], 3
; GCN1-NEXT:    s_add_u32 s0, s0, s4
; GCN1-NEXT:    s_addc_u32 s1, s1, s5
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_swap_x2 v[0:1], v[2:3], v[0:1] glc
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_xchg_i64_ret_addr64_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    s_lshl_b64 s[4:5], s[6:7], 3
; GCN2-NEXT:    s_add_u32 s0, s0, s4
; GCN2-NEXT:    s_addc_u32 s1, s1, s5
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_swap_x2 v[0:1], v[2:3], v[0:1] glc
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %gep = getelementptr i64, ptr %ptr, i64 4
  %tmp0 = atomicrmw volatile xchg ptr %gep, i64 %in seq_cst
  store i64 %tmp0, ptr %out2
  ret void
}

define amdgpu_kernel void @atomic_xchg_i64(ptr %out, i64 %in) {
; GCN1-LABEL: atomic_xchg_i64:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s0
; GCN1-NEXT:    v_mov_b32_e32 v1, s1
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_swap_x2 v[0:1], v[2:3]
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_xchg_i64:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s0
; GCN2-NEXT:    v_mov_b32_e32 v1, s1
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_swap_x2 v[0:1], v[2:3]
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    s_endpgm
entry:
  %tmp0 = atomicrmw volatile xchg ptr %out, i64 %in seq_cst
  ret void
}

define amdgpu_kernel void @atomic_xchg_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GCN1-LABEL: atomic_xchg_i64_ret:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN1-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_swap_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    v_mov_b32_e32 v2, s6
; GCN1-NEXT:    v_mov_b32_e32 v3, s7
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_xchg_i64_ret:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
; GCN2-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_swap_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    v_mov_b32_e32 v2, s6
; GCN2-NEXT:    v_mov_b32_e32 v3, s7
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %tmp0 = atomicrmw volatile xchg ptr %out, i64 %in seq_cst
  store i64 %tmp0, ptr %out2
  ret void
}

define amdgpu_kernel void @atomic_xchg_i64_addr64(ptr %out, i64 %in, i64 %index) {
; GCN1-LABEL: atomic_xchg_i64_addr64:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN1-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s6
; GCN1-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN1-NEXT:    s_add_u32 s0, s4, s0
; GCN1-NEXT:    s_addc_u32 s1, s5, s1
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v1, s7
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_swap_x2 v[2:3], v[0:1]
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_xchg_i64_addr64:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
; GCN2-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s6
; GCN2-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN2-NEXT:    s_add_u32 s0, s4, s0
; GCN2-NEXT:    s_addc_u32 s1, s5, s1
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v1, s7
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_swap_x2 v[2:3], v[0:1]
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %tmp0 = atomicrmw volatile xchg ptr %ptr, i64 %in seq_cst
  ret void
}

define amdgpu_kernel void @atomic_xchg_i64_ret_addr64(ptr %out, ptr %out2, i64 %in, i64 %index) {
; GCN1-LABEL: atomic_xchg_i64_ret_addr64:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    s_lshl_b64 s[4:5], s[6:7], 3
; GCN1-NEXT:    s_add_u32 s0, s0, s4
; GCN1-NEXT:    s_addc_u32 s1, s1, s5
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_swap_x2 v[0:1], v[2:3], v[0:1] glc
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_xchg_i64_ret_addr64:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    s_lshl_b64 s[4:5], s[6:7], 3
; GCN2-NEXT:    s_add_u32 s0, s0, s4
; GCN2-NEXT:    s_addc_u32 s1, s1, s5
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_swap_x2 v[0:1], v[2:3], v[0:1] glc
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %tmp0 = atomicrmw volatile xchg ptr %ptr, i64 %in seq_cst
  store i64 %tmp0, ptr %out2
  ret void
}

define amdgpu_kernel void @atomic_xor_i64_offset(ptr %out, i64 %in) {
; GCN1-LABEL: atomic_xor_i64_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v0, s2
; GCN1-NEXT:    v_mov_b32_e32 v1, s3
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_xor_x2 v[2:3], v[0:1]
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_xor_i64_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v0, s2
; GCN2-NEXT:    v_mov_b32_e32 v1, s3
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_xor_x2 v[2:3], v[0:1]
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    s_endpgm
entry:
  %gep = getelementptr i64, ptr %out, i64 4
  %tmp0 = atomicrmw volatile xor ptr %gep, i64 %in seq_cst
  ret void
}

define amdgpu_kernel void @atomic_xor_i64_ret_offset(ptr %out, ptr %out2, i64 %in) {
; GCN1-LABEL: atomic_xor_i64_ret_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xd
; GCN1-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_xor_x2 v[0:1], v[2:3], v[0:1] glc
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_xor_i64_ret_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x34
; GCN2-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_xor_x2 v[0:1], v[2:3], v[0:1] glc
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %gep = getelementptr i64, ptr %out, i64 4
  %tmp0 = atomicrmw volatile xor ptr %gep, i64 %in seq_cst
  store i64 %tmp0, ptr %out2
  ret void
}

define amdgpu_kernel void @atomic_xor_i64_addr64_offset(ptr %out, i64 %in, i64 %index) {
; GCN1-LABEL: atomic_xor_i64_addr64_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN1-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s6
; GCN1-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN1-NEXT:    s_add_u32 s0, s4, s0
; GCN1-NEXT:    s_addc_u32 s1, s5, s1
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v1, s7
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_xor_x2 v[2:3], v[0:1]
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_xor_i64_addr64_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
; GCN2-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s6
; GCN2-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN2-NEXT:    s_add_u32 s0, s4, s0
; GCN2-NEXT:    s_addc_u32 s1, s5, s1
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v1, s7
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_xor_x2 v[2:3], v[0:1]
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %gep = getelementptr i64, ptr %ptr, i64 4
  %tmp0 = atomicrmw volatile xor ptr %gep, i64 %in seq_cst
  ret void
}

define amdgpu_kernel void @atomic_xor_i64_ret_addr64_offset(ptr %out, ptr %out2, i64 %in, i64 %index) {
; GCN1-LABEL: atomic_xor_i64_ret_addr64_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    s_lshl_b64 s[4:5], s[6:7], 3
; GCN1-NEXT:    s_add_u32 s0, s0, s4
; GCN1-NEXT:    s_addc_u32 s1, s1, s5
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_xor_x2 v[0:1], v[2:3], v[0:1] glc
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_xor_i64_ret_addr64_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    s_lshl_b64 s[4:5], s[6:7], 3
; GCN2-NEXT:    s_add_u32 s0, s0, s4
; GCN2-NEXT:    s_addc_u32 s1, s1, s5
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_xor_x2 v[0:1], v[2:3], v[0:1] glc
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %gep = getelementptr i64, ptr %ptr, i64 4
  %tmp0 = atomicrmw volatile xor ptr %gep, i64 %in seq_cst
  store i64 %tmp0, ptr %out2
  ret void
}

define amdgpu_kernel void @atomic_xor_i64(ptr %out, i64 %in) {
; GCN1-LABEL: atomic_xor_i64:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s0
; GCN1-NEXT:    v_mov_b32_e32 v1, s1
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_xor_x2 v[0:1], v[2:3]
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_xor_i64:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s0
; GCN2-NEXT:    v_mov_b32_e32 v1, s1
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_xor_x2 v[0:1], v[2:3]
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    s_endpgm
entry:
  %tmp0 = atomicrmw volatile xor ptr %out, i64 %in seq_cst
  ret void
}

define amdgpu_kernel void @atomic_xor_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GCN1-LABEL: atomic_xor_i64_ret:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN1-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_xor_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    v_mov_b32_e32 v2, s6
; GCN1-NEXT:    v_mov_b32_e32 v3, s7
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_xor_i64_ret:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
; GCN2-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_xor_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    v_mov_b32_e32 v2, s6
; GCN2-NEXT:    v_mov_b32_e32 v3, s7
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %tmp0 = atomicrmw volatile xor ptr %out, i64 %in seq_cst
  store i64 %tmp0, ptr %out2
  ret void
}

define amdgpu_kernel void @atomic_xor_i64_addr64(ptr %out, i64 %in, i64 %index) {
; GCN1-LABEL: atomic_xor_i64_addr64:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN1-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s6
; GCN1-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN1-NEXT:    s_add_u32 s0, s4, s0
; GCN1-NEXT:    s_addc_u32 s1, s5, s1
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v1, s7
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_xor_x2 v[2:3], v[0:1]
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_xor_i64_addr64:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
; GCN2-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s6
; GCN2-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN2-NEXT:    s_add_u32 s0, s4, s0
; GCN2-NEXT:    s_addc_u32 s1, s5, s1
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v1, s7
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_xor_x2 v[2:3], v[0:1]
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %tmp0 = atomicrmw volatile xor ptr %ptr, i64 %in seq_cst
  ret void
}

define amdgpu_kernel void @atomic_xor_i64_ret_addr64(ptr %out, ptr %out2, i64 %in, i64 %index) {
; GCN1-LABEL: atomic_xor_i64_ret_addr64:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    s_lshl_b64 s[4:5], s[6:7], 3
; GCN1-NEXT:    s_add_u32 s0, s0, s4
; GCN1-NEXT:    s_addc_u32 s1, s1, s5
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_xor_x2 v[0:1], v[2:3], v[0:1] glc
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_xor_i64_ret_addr64:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    s_lshl_b64 s[4:5], s[6:7], 3
; GCN2-NEXT:    s_add_u32 s0, s0, s4
; GCN2-NEXT:    s_addc_u32 s1, s1, s5
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_xor_x2 v[0:1], v[2:3], v[0:1] glc
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %tmp0 = atomicrmw volatile xor ptr %ptr, i64 %in seq_cst
  store i64 %tmp0, ptr %out2
  ret void
}

define amdgpu_kernel void @atomic_load_i64_offset(ptr %in, ptr %out) {
; GCN1-LABEL: atomic_load_i64_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v0, s0
; GCN1-NEXT:    v_mov_b32_e32 v1, s1
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_load_dwordx2 v[0:1], v[0:1] glc
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_load_i64_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v0, s0
; GCN2-NEXT:    v_mov_b32_e32 v1, s1
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_load_dwordx2 v[0:1], v[0:1] glc
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %gep = getelementptr i64, ptr %in, i64 4
  %val = load atomic i64, ptr %gep  seq_cst, align 8
  store i64 %val, ptr %out
  ret void
}

define amdgpu_kernel void @atomic_load_i64(ptr %in, ptr %out) {
; GCN1-LABEL: atomic_load_i64:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s0
; GCN1-NEXT:    v_mov_b32_e32 v1, s1
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_load_dwordx2 v[0:1], v[0:1] glc
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_load_i64:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s0
; GCN2-NEXT:    v_mov_b32_e32 v1, s1
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_load_dwordx2 v[0:1], v[0:1] glc
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %val = load atomic i64, ptr %in seq_cst, align 8
  store i64 %val, ptr %out
  ret void
}

define amdgpu_kernel void @atomic_load_i64_addr64_offset(ptr %in, ptr %out, i64 %index) {
; GCN1-LABEL: atomic_load_i64_addr64_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xd
; GCN1-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    s_lshl_b64 s[4:5], s[4:5], 3
; GCN1-NEXT:    s_add_u32 s0, s0, s4
; GCN1-NEXT:    s_addc_u32 s1, s1, s5
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v0, s0
; GCN1-NEXT:    v_mov_b32_e32 v1, s1
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_load_dwordx2 v[0:1], v[0:1] glc
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_load_i64_addr64_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x34
; GCN2-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    s_lshl_b64 s[4:5], s[4:5], 3
; GCN2-NEXT:    s_add_u32 s0, s0, s4
; GCN2-NEXT:    s_addc_u32 s1, s1, s5
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v0, s0
; GCN2-NEXT:    v_mov_b32_e32 v1, s1
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_load_dwordx2 v[0:1], v[0:1] glc
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %in, i64 %index
  %gep = getelementptr i64, ptr %ptr, i64 4
  %val = load atomic i64, ptr %gep seq_cst, align 8
  store i64 %val, ptr %out
  ret void
}

define amdgpu_kernel void @atomic_load_i64_addr64(ptr %in, ptr %out, i64 %index) {
; GCN1-LABEL: atomic_load_i64_addr64:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xd
; GCN1-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    s_lshl_b64 s[4:5], s[4:5], 3
; GCN1-NEXT:    s_add_u32 s0, s0, s4
; GCN1-NEXT:    s_addc_u32 s1, s1, s5
; GCN1-NEXT:    v_mov_b32_e32 v0, s0
; GCN1-NEXT:    v_mov_b32_e32 v1, s1
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_load_dwordx2 v[0:1], v[0:1] glc
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_load_i64_addr64:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x34
; GCN2-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    s_lshl_b64 s[4:5], s[4:5], 3
; GCN2-NEXT:    s_add_u32 s0, s0, s4
; GCN2-NEXT:    s_addc_u32 s1, s1, s5
; GCN2-NEXT:    v_mov_b32_e32 v0, s0
; GCN2-NEXT:    v_mov_b32_e32 v1, s1
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_load_dwordx2 v[0:1], v[0:1] glc
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %in, i64 %index
  %val = load atomic i64, ptr %ptr seq_cst, align 8
  store i64 %val, ptr %out
  ret void
}

define amdgpu_kernel void @atomic_store_i64_offset(i64 %in, ptr %out) {
; GCN1-LABEL: atomic_store_i64_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s0
; GCN1-NEXT:    s_add_u32 s0, s2, 32
; GCN1-NEXT:    v_mov_b32_e32 v1, s1
; GCN1-NEXT:    s_addc_u32 s1, s3, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_store_i64_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s0
; GCN2-NEXT:    s_add_u32 s0, s2, 32
; GCN2-NEXT:    v_mov_b32_e32 v1, s1
; GCN2-NEXT:    s_addc_u32 s1, s3, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %gep = getelementptr i64, ptr %out, i64 4
  store atomic i64 %in, ptr %gep  seq_cst, align 8
  ret void
}

define amdgpu_kernel void @atomic_store_i64(i64 %in, ptr %out) {
; GCN1-LABEL: atomic_store_i64:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s0
; GCN1-NEXT:    v_mov_b32_e32 v1, s1
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_store_i64:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s0
; GCN2-NEXT:    v_mov_b32_e32 v1, s1
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  store atomic i64 %in, ptr %out seq_cst, align 8
  ret void
}

define amdgpu_kernel void @atomic_store_i64_addr64_offset(i64 %in, ptr %out, i64 %index) {
; GCN1-LABEL: atomic_store_i64_addr64_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN1-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN1-NEXT:    s_add_u32 s0, s6, s0
; GCN1-NEXT:    s_addc_u32 s1, s7, s1
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_store_i64_addr64_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
; GCN2-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN2-NEXT:    s_add_u32 s0, s6, s0
; GCN2-NEXT:    s_addc_u32 s1, s7, s1
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %gep = getelementptr i64, ptr %ptr, i64 4
  store atomic i64 %in, ptr %gep seq_cst, align 8
  ret void
}

define amdgpu_kernel void @atomic_store_i64_addr64(i64 %in, ptr %out, i64 %index) {
; GCN1-LABEL: atomic_store_i64_addr64:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN1-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN1-NEXT:    s_add_u32 s0, s6, s0
; GCN1-NEXT:    s_addc_u32 s1, s7, s1
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_store_i64_addr64:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
; GCN2-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN2-NEXT:    s_add_u32 s0, s6, s0
; GCN2-NEXT:    s_addc_u32 s1, s7, s1
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  store atomic i64 %in, ptr %ptr seq_cst, align 8
  ret void
}

define amdgpu_kernel void @atomic_cmpxchg_i64_offset(ptr %out, i64 %in, i64 %old) {
; GCN1-LABEL: atomic_cmpxchg_i64_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN1-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    s_add_u32 s2, s4, 32
; GCN1-NEXT:    s_addc_u32 s3, s5, 0
; GCN1-NEXT:    v_mov_b32_e32 v5, s3
; GCN1-NEXT:    v_mov_b32_e32 v0, s6
; GCN1-NEXT:    v_mov_b32_e32 v1, s7
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v4, s2
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_cmpswap_x2 v[4:5], v[0:3]
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_cmpxchg_i64_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
; GCN2-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    s_add_u32 s2, s4, 32
; GCN2-NEXT:    s_addc_u32 s3, s5, 0
; GCN2-NEXT:    v_mov_b32_e32 v5, s3
; GCN2-NEXT:    v_mov_b32_e32 v0, s6
; GCN2-NEXT:    v_mov_b32_e32 v1, s7
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v4, s2
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_cmpswap_x2 v[4:5], v[0:3]
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    s_endpgm
entry:
  %gep = getelementptr i64, ptr %out, i64 4
  %val = cmpxchg volatile ptr %gep, i64 %old, i64 %in seq_cst seq_cst
  ret void
}

define amdgpu_kernel void @atomic_cmpxchg_i64_soffset(ptr %out, i64 %in, i64 %old) {
; GCN1-LABEL: atomic_cmpxchg_i64_soffset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN1-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    s_add_u32 s2, s4, 0x11940
; GCN1-NEXT:    s_addc_u32 s3, s5, 0
; GCN1-NEXT:    v_mov_b32_e32 v5, s3
; GCN1-NEXT:    v_mov_b32_e32 v0, s6
; GCN1-NEXT:    v_mov_b32_e32 v1, s7
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v4, s2
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_cmpswap_x2 v[4:5], v[0:3]
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_cmpxchg_i64_soffset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
; GCN2-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    s_add_u32 s2, s4, 0x11940
; GCN2-NEXT:    s_addc_u32 s3, s5, 0
; GCN2-NEXT:    v_mov_b32_e32 v5, s3
; GCN2-NEXT:    v_mov_b32_e32 v0, s6
; GCN2-NEXT:    v_mov_b32_e32 v1, s7
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v4, s2
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_cmpswap_x2 v[4:5], v[0:3]
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    s_endpgm
entry:
  %gep = getelementptr i64, ptr %out, i64 9000
  %val = cmpxchg volatile ptr %gep, i64 %old, i64 %in seq_cst seq_cst
  ret void
}

define amdgpu_kernel void @atomic_cmpxchg_i64_ret_offset(ptr %out, ptr %out2, i64 %in, i64 %old) {
; GCN1-LABEL: atomic_cmpxchg_i64_ret_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v5, s1
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    v_mov_b32_e32 v2, s6
; GCN1-NEXT:    v_mov_b32_e32 v3, s7
; GCN1-NEXT:    v_mov_b32_e32 v4, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_cmpxchg_i64_ret_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v5, s1
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    v_mov_b32_e32 v2, s6
; GCN2-NEXT:    v_mov_b32_e32 v3, s7
; GCN2-NEXT:    v_mov_b32_e32 v4, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %gep = getelementptr i64, ptr %out, i64 4
  %val = cmpxchg volatile ptr %gep, i64 %old, i64 %in seq_cst seq_cst
  %extract0 = extractvalue { i64, i1 } %val, 0
  store i64 %extract0, ptr %out2
  ret void
}

define amdgpu_kernel void @atomic_cmpxchg_i64_addr64_offset(ptr %out, i64 %in, i64 %index, i64 %old) {
; GCN1-LABEL: atomic_cmpxchg_i64_addr64_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    s_lshl_b64 s[4:5], s[4:5], 3
; GCN1-NEXT:    s_add_u32 s0, s0, s4
; GCN1-NEXT:    s_addc_u32 s1, s1, s5
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v5, s1
; GCN1-NEXT:    v_mov_b32_e32 v0, s2
; GCN1-NEXT:    v_mov_b32_e32 v1, s3
; GCN1-NEXT:    v_mov_b32_e32 v2, s6
; GCN1-NEXT:    v_mov_b32_e32 v3, s7
; GCN1-NEXT:    v_mov_b32_e32 v4, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_cmpswap_x2 v[4:5], v[0:3]
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_cmpxchg_i64_addr64_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    s_lshl_b64 s[4:5], s[4:5], 3
; GCN2-NEXT:    s_add_u32 s0, s0, s4
; GCN2-NEXT:    s_addc_u32 s1, s1, s5
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v5, s1
; GCN2-NEXT:    v_mov_b32_e32 v0, s2
; GCN2-NEXT:    v_mov_b32_e32 v1, s3
; GCN2-NEXT:    v_mov_b32_e32 v2, s6
; GCN2-NEXT:    v_mov_b32_e32 v3, s7
; GCN2-NEXT:    v_mov_b32_e32 v4, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_cmpswap_x2 v[4:5], v[0:3]
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %gep = getelementptr i64, ptr %ptr, i64 4
  %val = cmpxchg volatile ptr %gep, i64 %old, i64 %in seq_cst seq_cst
  ret void
}

define amdgpu_kernel void @atomic_cmpxchg_i64_ret_addr64_offset(ptr %out, ptr %out2, i64 %in, i64 %index, i64 %old) {
; GCN1-LABEL: atomic_cmpxchg_i64_ret_addr64_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x9
; GCN1-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x11
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    s_lshl_b64 s[2:3], s[10:11], 3
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_add_u32 s0, s4, s2
; GCN1-NEXT:    s_addc_u32 s3, s5, s3
; GCN1-NEXT:    s_add_u32 s2, s0, 32
; GCN1-NEXT:    s_addc_u32 s3, s3, 0
; GCN1-NEXT:    v_mov_b32_e32 v5, s3
; GCN1-NEXT:    v_mov_b32_e32 v0, s8
; GCN1-NEXT:    v_mov_b32_e32 v1, s9
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v4, s2
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    v_mov_b32_e32 v2, s6
; GCN1-NEXT:    v_mov_b32_e32 v3, s7
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_cmpxchg_i64_ret_addr64_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x24
; GCN2-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x44
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    s_lshl_b64 s[2:3], s[10:11], 3
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_add_u32 s0, s4, s2
; GCN2-NEXT:    s_addc_u32 s3, s5, s3
; GCN2-NEXT:    s_add_u32 s2, s0, 32
; GCN2-NEXT:    s_addc_u32 s3, s3, 0
; GCN2-NEXT:    v_mov_b32_e32 v5, s3
; GCN2-NEXT:    v_mov_b32_e32 v0, s8
; GCN2-NEXT:    v_mov_b32_e32 v1, s9
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v4, s2
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    v_mov_b32_e32 v2, s6
; GCN2-NEXT:    v_mov_b32_e32 v3, s7
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %gep = getelementptr i64, ptr %ptr, i64 4
  %val = cmpxchg volatile ptr %gep, i64 %old, i64 %in seq_cst seq_cst
  %extract0 = extractvalue { i64, i1 } %val, 0
  store i64 %extract0, ptr %out2
  ret void
}

define amdgpu_kernel void @atomic_cmpxchg_i64(ptr %out, i64 %in, i64 %old) {
; GCN1-LABEL: atomic_cmpxchg_i64:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN1-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v4, s4
; GCN1-NEXT:    v_mov_b32_e32 v5, s5
; GCN1-NEXT:    v_mov_b32_e32 v0, s6
; GCN1-NEXT:    v_mov_b32_e32 v1, s7
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_cmpswap_x2 v[4:5], v[0:3]
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_cmpxchg_i64:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
; GCN2-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v4, s4
; GCN2-NEXT:    v_mov_b32_e32 v5, s5
; GCN2-NEXT:    v_mov_b32_e32 v0, s6
; GCN2-NEXT:    v_mov_b32_e32 v1, s7
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_cmpswap_x2 v[4:5], v[0:3]
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    s_endpgm
entry:
  %val = cmpxchg volatile ptr %out, i64 %old, i64 %in seq_cst seq_cst
  ret void
}

define amdgpu_kernel void @atomic_cmpxchg_i64_ret(ptr %out, ptr %out2, i64 %in, i64 %old) {
; GCN1-LABEL: atomic_cmpxchg_i64_ret:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v4, s0
; GCN1-NEXT:    v_mov_b32_e32 v5, s1
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    v_mov_b32_e32 v2, s6
; GCN1-NEXT:    v_mov_b32_e32 v3, s7
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_cmpxchg_i64_ret:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v4, s0
; GCN2-NEXT:    v_mov_b32_e32 v5, s1
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    v_mov_b32_e32 v2, s6
; GCN2-NEXT:    v_mov_b32_e32 v3, s7
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %val = cmpxchg volatile ptr %out, i64 %old, i64 %in seq_cst seq_cst
  %extract0 = extractvalue { i64, i1 } %val, 0
  store i64 %extract0, ptr %out2
  ret void
}

define amdgpu_kernel void @atomic_cmpxchg_i64_addr64(ptr %out, i64 %in, i64 %index, i64 %old) {
; GCN1-LABEL: atomic_cmpxchg_i64_addr64:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    s_lshl_b64 s[4:5], s[4:5], 3
; GCN1-NEXT:    s_add_u32 s0, s0, s4
; GCN1-NEXT:    s_addc_u32 s1, s1, s5
; GCN1-NEXT:    v_mov_b32_e32 v5, s1
; GCN1-NEXT:    v_mov_b32_e32 v0, s2
; GCN1-NEXT:    v_mov_b32_e32 v1, s3
; GCN1-NEXT:    v_mov_b32_e32 v2, s6
; GCN1-NEXT:    v_mov_b32_e32 v3, s7
; GCN1-NEXT:    v_mov_b32_e32 v4, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_cmpswap_x2 v[4:5], v[0:3]
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_cmpxchg_i64_addr64:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    s_lshl_b64 s[4:5], s[4:5], 3
; GCN2-NEXT:    s_add_u32 s0, s0, s4
; GCN2-NEXT:    s_addc_u32 s1, s1, s5
; GCN2-NEXT:    v_mov_b32_e32 v5, s1
; GCN2-NEXT:    v_mov_b32_e32 v0, s2
; GCN2-NEXT:    v_mov_b32_e32 v1, s3
; GCN2-NEXT:    v_mov_b32_e32 v2, s6
; GCN2-NEXT:    v_mov_b32_e32 v3, s7
; GCN2-NEXT:    v_mov_b32_e32 v4, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_cmpswap_x2 v[4:5], v[0:3]
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %val = cmpxchg volatile ptr %ptr, i64 %old, i64 %in seq_cst seq_cst
  ret void
}

define amdgpu_kernel void @atomic_cmpxchg_i64_ret_addr64(ptr %out, ptr %out2, i64 %in, i64 %index, i64 %old) {
; GCN1-LABEL: atomic_cmpxchg_i64_ret_addr64:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x9
; GCN1-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x11
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    s_lshl_b64 s[2:3], s[10:11], 3
; GCN1-NEXT:    s_add_u32 s2, s4, s2
; GCN1-NEXT:    s_addc_u32 s3, s5, s3
; GCN1-NEXT:    v_mov_b32_e32 v5, s3
; GCN1-NEXT:    v_mov_b32_e32 v0, s8
; GCN1-NEXT:    v_mov_b32_e32 v1, s9
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v4, s2
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    v_mov_b32_e32 v2, s6
; GCN1-NEXT:    v_mov_b32_e32 v3, s7
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_cmpxchg_i64_ret_addr64:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x24
; GCN2-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x44
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    s_lshl_b64 s[2:3], s[10:11], 3
; GCN2-NEXT:    s_add_u32 s2, s4, s2
; GCN2-NEXT:    s_addc_u32 s3, s5, s3
; GCN2-NEXT:    v_mov_b32_e32 v5, s3
; GCN2-NEXT:    v_mov_b32_e32 v0, s8
; GCN2-NEXT:    v_mov_b32_e32 v1, s9
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v4, s2
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    v_mov_b32_e32 v2, s6
; GCN2-NEXT:    v_mov_b32_e32 v3, s7
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %val = cmpxchg volatile ptr %ptr, i64 %old, i64 %in seq_cst seq_cst
  %extract0 = extractvalue { i64, i1 } %val, 0
  store i64 %extract0, ptr %out2
  ret void
}

define amdgpu_kernel void @atomic_load_f64_offset(ptr %in, ptr %out) {
; GCN1-LABEL: atomic_load_f64_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v0, s0
; GCN1-NEXT:    v_mov_b32_e32 v1, s1
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_load_dwordx2 v[0:1], v[0:1] glc
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_load_f64_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v0, s0
; GCN2-NEXT:    v_mov_b32_e32 v1, s1
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_load_dwordx2 v[0:1], v[0:1] glc
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %gep = getelementptr double, ptr %in, i64 4
  %val = load atomic double, ptr %gep  seq_cst, align 8
  store double %val, ptr %out
  ret void
}

define amdgpu_kernel void @atomic_load_f64(ptr %in, ptr %out) {
; GCN1-LABEL: atomic_load_f64:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s0
; GCN1-NEXT:    v_mov_b32_e32 v1, s1
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_load_dwordx2 v[0:1], v[0:1] glc
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_load_f64:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s0
; GCN2-NEXT:    v_mov_b32_e32 v1, s1
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_load_dwordx2 v[0:1], v[0:1] glc
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %val = load atomic double, ptr %in seq_cst, align 8
  store double %val, ptr %out
  ret void
}

define amdgpu_kernel void @atomic_load_f64_addr64_offset(ptr %in, ptr %out, i64 %index) {
; GCN1-LABEL: atomic_load_f64_addr64_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xd
; GCN1-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    s_lshl_b64 s[4:5], s[4:5], 3
; GCN1-NEXT:    s_add_u32 s0, s0, s4
; GCN1-NEXT:    s_addc_u32 s1, s1, s5
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v0, s0
; GCN1-NEXT:    v_mov_b32_e32 v1, s1
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_load_dwordx2 v[0:1], v[0:1] glc
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_load_f64_addr64_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x34
; GCN2-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    s_lshl_b64 s[4:5], s[4:5], 3
; GCN2-NEXT:    s_add_u32 s0, s0, s4
; GCN2-NEXT:    s_addc_u32 s1, s1, s5
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v0, s0
; GCN2-NEXT:    v_mov_b32_e32 v1, s1
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_load_dwordx2 v[0:1], v[0:1] glc
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr double, ptr %in, i64 %index
  %gep = getelementptr double, ptr %ptr, i64 4
  %val = load atomic double, ptr %gep seq_cst, align 8
  store double %val, ptr %out
  ret void
}

define amdgpu_kernel void @atomic_load_f64_addr64(ptr %in, ptr %out, i64 %index) {
; GCN1-LABEL: atomic_load_f64_addr64:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xd
; GCN1-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    s_lshl_b64 s[4:5], s[4:5], 3
; GCN1-NEXT:    s_add_u32 s0, s0, s4
; GCN1-NEXT:    s_addc_u32 s1, s1, s5
; GCN1-NEXT:    v_mov_b32_e32 v0, s0
; GCN1-NEXT:    v_mov_b32_e32 v1, s1
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_load_dwordx2 v[0:1], v[0:1] glc
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_load_f64_addr64:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x34
; GCN2-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    s_lshl_b64 s[4:5], s[4:5], 3
; GCN2-NEXT:    s_add_u32 s0, s0, s4
; GCN2-NEXT:    s_addc_u32 s1, s1, s5
; GCN2-NEXT:    v_mov_b32_e32 v0, s0
; GCN2-NEXT:    v_mov_b32_e32 v1, s1
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_load_dwordx2 v[0:1], v[0:1] glc
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr double, ptr %in, i64 %index
  %val = load atomic double, ptr %ptr seq_cst, align 8
  store double %val, ptr %out
  ret void
}

define amdgpu_kernel void @atomic_store_f64_offset(double %in, ptr %out) {
; GCN1-LABEL: atomic_store_f64_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s0
; GCN1-NEXT:    s_add_u32 s0, s2, 32
; GCN1-NEXT:    v_mov_b32_e32 v1, s1
; GCN1-NEXT:    s_addc_u32 s1, s3, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_store_f64_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s0
; GCN2-NEXT:    s_add_u32 s0, s2, 32
; GCN2-NEXT:    v_mov_b32_e32 v1, s1
; GCN2-NEXT:    s_addc_u32 s1, s3, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %gep = getelementptr double, ptr %out, i64 4
  store atomic double %in, ptr %gep  seq_cst, align 8
  ret void
}

define amdgpu_kernel void @atomic_store_f64(double %in, ptr %out) {
; GCN1-LABEL: atomic_store_f64:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s0
; GCN1-NEXT:    v_mov_b32_e32 v1, s1
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_store_f64:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s0
; GCN2-NEXT:    v_mov_b32_e32 v1, s1
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  store atomic double %in, ptr %out seq_cst, align 8
  ret void
}

define amdgpu_kernel void @atomic_store_f64_addr64_offset(double %in, ptr %out, i64 %index) {
; GCN1-LABEL: atomic_store_f64_addr64_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN1-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN1-NEXT:    s_add_u32 s0, s6, s0
; GCN1-NEXT:    s_addc_u32 s1, s7, s1
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_store_f64_addr64_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
; GCN2-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN2-NEXT:    s_add_u32 s0, s6, s0
; GCN2-NEXT:    s_addc_u32 s1, s7, s1
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr double, ptr %out, i64 %index
  %gep = getelementptr double, ptr %ptr, i64 4
  store atomic double %in, ptr %gep seq_cst, align 8
  ret void
}

define amdgpu_kernel void @atomic_store_f64_addr64(double %in, ptr %out, i64 %index) {
; GCN1-LABEL: atomic_store_f64_addr64:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN1-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN1-NEXT:    s_add_u32 s0, s6, s0
; GCN1-NEXT:    s_addc_u32 s1, s7, s1
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_store_f64_addr64:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
; GCN2-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN2-NEXT:    s_add_u32 s0, s6, s0
; GCN2-NEXT:    s_addc_u32 s1, s7, s1
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr double, ptr %out, i64 %index
  store atomic double %in, ptr %ptr seq_cst, align 8
  ret void
}

define amdgpu_kernel void @atomic_inc_i64_offset(ptr %out, i64 %in) {
; GCN1-LABEL: atomic_inc_i64_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v0, s2
; GCN1-NEXT:    v_mov_b32_e32 v1, s3
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_inc_x2 v[2:3], v[0:1]
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_inc_i64_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v0, s2
; GCN2-NEXT:    v_mov_b32_e32 v1, s3
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_inc_x2 v[2:3], v[0:1]
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    s_endpgm
entry:
  %gep = getelementptr i64, ptr %out, i64 4
  %tmp0 = atomicrmw volatile uinc_wrap ptr %gep, i64 %in seq_cst
  ret void
}

define amdgpu_kernel void @atomic_inc_i64_ret_offset(ptr %out, ptr %out2, i64 %in) {
; GCN1-LABEL: atomic_inc_i64_ret_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xd
; GCN1-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_inc_x2 v[0:1], v[2:3], v[0:1] glc
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_inc_i64_ret_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x34
; GCN2-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_inc_x2 v[0:1], v[2:3], v[0:1] glc
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %gep = getelementptr i64, ptr %out, i64 4
  %tmp0 = atomicrmw volatile uinc_wrap ptr %gep, i64 %in seq_cst
  store i64 %tmp0, ptr %out2
  ret void
}

define amdgpu_kernel void @atomic_inc_i64_incr64_offset(ptr %out, i64 %in, i64 %index) {
; GCN1-LABEL: atomic_inc_i64_incr64_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN1-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s6
; GCN1-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN1-NEXT:    s_add_u32 s0, s4, s0
; GCN1-NEXT:    s_addc_u32 s1, s5, s1
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v1, s7
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_inc_x2 v[2:3], v[0:1]
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_inc_i64_incr64_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
; GCN2-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s6
; GCN2-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN2-NEXT:    s_add_u32 s0, s4, s0
; GCN2-NEXT:    s_addc_u32 s1, s5, s1
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v1, s7
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_inc_x2 v[2:3], v[0:1]
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %gep = getelementptr i64, ptr %ptr, i64 4
  %tmp0 = atomicrmw volatile uinc_wrap ptr %gep, i64 %in seq_cst
  ret void
}

define amdgpu_kernel void @atomic_inc_i64_ret_incr64_offset(ptr %out, ptr %out2, i64 %in, i64 %index) {
; GCN1-LABEL: atomic_inc_i64_ret_incr64_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    s_lshl_b64 s[4:5], s[6:7], 3
; GCN1-NEXT:    s_add_u32 s0, s0, s4
; GCN1-NEXT:    s_addc_u32 s1, s1, s5
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_inc_x2 v[0:1], v[2:3], v[0:1] glc
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_inc_i64_ret_incr64_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    s_lshl_b64 s[4:5], s[6:7], 3
; GCN2-NEXT:    s_add_u32 s0, s0, s4
; GCN2-NEXT:    s_addc_u32 s1, s1, s5
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_inc_x2 v[0:1], v[2:3], v[0:1] glc
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %gep = getelementptr i64, ptr %ptr, i64 4
  %tmp0 = atomicrmw volatile uinc_wrap ptr %gep, i64 %in seq_cst
  store i64 %tmp0, ptr %out2
  ret void
}

define amdgpu_kernel void @atomic_inc_i64(ptr %out, i64 %in) {
; GCN1-LABEL: atomic_inc_i64:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s0
; GCN1-NEXT:    v_mov_b32_e32 v1, s1
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_inc_x2 v[0:1], v[2:3]
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_inc_i64:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s0
; GCN2-NEXT:    v_mov_b32_e32 v1, s1
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_inc_x2 v[0:1], v[2:3]
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    s_endpgm
entry:
  %tmp0 = atomicrmw volatile uinc_wrap ptr %out, i64 %in seq_cst
  ret void
}

define amdgpu_kernel void @atomic_inc_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GCN1-LABEL: atomic_inc_i64_ret:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN1-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    v_mov_b32_e32 v2, s6
; GCN1-NEXT:    v_mov_b32_e32 v3, s7
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_inc_i64_ret:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
; GCN2-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    v_mov_b32_e32 v2, s6
; GCN2-NEXT:    v_mov_b32_e32 v3, s7
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %tmp0 = atomicrmw volatile uinc_wrap ptr %out, i64 %in seq_cst
  store i64 %tmp0, ptr %out2
  ret void
}

define amdgpu_kernel void @atomic_inc_i64_incr64(ptr %out, i64 %in, i64 %index) {
; GCN1-LABEL: atomic_inc_i64_incr64:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN1-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s6
; GCN1-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN1-NEXT:    s_add_u32 s0, s4, s0
; GCN1-NEXT:    s_addc_u32 s1, s5, s1
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v1, s7
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_inc_x2 v[2:3], v[0:1]
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_inc_i64_incr64:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
; GCN2-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s6
; GCN2-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN2-NEXT:    s_add_u32 s0, s4, s0
; GCN2-NEXT:    s_addc_u32 s1, s5, s1
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v1, s7
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_inc_x2 v[2:3], v[0:1]
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %tmp0 = atomicrmw volatile uinc_wrap ptr %ptr, i64 %in seq_cst
  ret void
}

define amdgpu_kernel void @atomic_inc_i64_ret_incr64(ptr %out, ptr %out2, i64 %in, i64 %index) {
; GCN1-LABEL: atomic_inc_i64_ret_incr64:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    s_lshl_b64 s[4:5], s[6:7], 3
; GCN1-NEXT:    s_add_u32 s0, s0, s4
; GCN1-NEXT:    s_addc_u32 s1, s1, s5
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_inc_x2 v[0:1], v[2:3], v[0:1] glc
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_inc_i64_ret_incr64:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    s_lshl_b64 s[4:5], s[6:7], 3
; GCN2-NEXT:    s_add_u32 s0, s0, s4
; GCN2-NEXT:    s_addc_u32 s1, s1, s5
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_inc_x2 v[0:1], v[2:3], v[0:1] glc
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %tmp0 = atomicrmw volatile uinc_wrap ptr %ptr, i64 %in seq_cst
  store i64 %tmp0, ptr %out2
  ret void
}

define amdgpu_kernel void @atomic_dec_i64_offset(ptr %out, i64 %in) {
; GCN1-LABEL: atomic_dec_i64_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v0, s2
; GCN1-NEXT:    v_mov_b32_e32 v1, s3
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_dec_x2 v[2:3], v[0:1]
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_dec_i64_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v0, s2
; GCN2-NEXT:    v_mov_b32_e32 v1, s3
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_dec_x2 v[2:3], v[0:1]
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    s_endpgm
entry:
  %gep = getelementptr i64, ptr %out, i64 4
  %tmp0 = atomicrmw volatile udec_wrap ptr %gep, i64 %in seq_cst
  ret void
}

define amdgpu_kernel void @atomic_dec_i64_ret_offset(ptr %out, ptr %out2, i64 %in) {
; GCN1-LABEL: atomic_dec_i64_ret_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xd
; GCN1-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_dec_x2 v[0:1], v[2:3], v[0:1] glc
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_dec_i64_ret_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x34
; GCN2-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_dec_x2 v[0:1], v[2:3], v[0:1] glc
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %gep = getelementptr i64, ptr %out, i64 4
  %tmp0 = atomicrmw volatile udec_wrap ptr %gep, i64 %in seq_cst
  store i64 %tmp0, ptr %out2
  ret void
}

define amdgpu_kernel void @atomic_dec_i64_decr64_offset(ptr %out, i64 %in, i64 %index) {
; GCN1-LABEL: atomic_dec_i64_decr64_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN1-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s6
; GCN1-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN1-NEXT:    s_add_u32 s0, s4, s0
; GCN1-NEXT:    s_addc_u32 s1, s5, s1
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v1, s7
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_dec_x2 v[2:3], v[0:1]
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_dec_i64_decr64_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
; GCN2-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s6
; GCN2-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN2-NEXT:    s_add_u32 s0, s4, s0
; GCN2-NEXT:    s_addc_u32 s1, s5, s1
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v1, s7
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_dec_x2 v[2:3], v[0:1]
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %gep = getelementptr i64, ptr %ptr, i64 4
  %tmp0 = atomicrmw volatile udec_wrap ptr %gep, i64 %in seq_cst
  ret void
}

define amdgpu_kernel void @atomic_dec_i64_ret_decr64_offset(ptr %out, ptr %out2, i64 %in, i64 %index) {
; GCN1-LABEL: atomic_dec_i64_ret_decr64_offset:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    s_lshl_b64 s[4:5], s[6:7], 3
; GCN1-NEXT:    s_add_u32 s0, s0, s4
; GCN1-NEXT:    s_addc_u32 s1, s1, s5
; GCN1-NEXT:    s_add_u32 s0, s0, 32
; GCN1-NEXT:    s_addc_u32 s1, s1, 0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_dec_x2 v[0:1], v[2:3], v[0:1] glc
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_dec_i64_ret_decr64_offset:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    s_lshl_b64 s[4:5], s[6:7], 3
; GCN2-NEXT:    s_add_u32 s0, s0, s4
; GCN2-NEXT:    s_addc_u32 s1, s1, s5
; GCN2-NEXT:    s_add_u32 s0, s0, 32
; GCN2-NEXT:    s_addc_u32 s1, s1, 0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_dec_x2 v[0:1], v[2:3], v[0:1] glc
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %gep = getelementptr i64, ptr %ptr, i64 4
  %tmp0 = atomicrmw volatile udec_wrap ptr %gep, i64 %in seq_cst
  store i64 %tmp0, ptr %out2
  ret void
}

define amdgpu_kernel void @atomic_dec_i64(ptr %out, i64 %in) {
; GCN1-LABEL: atomic_dec_i64:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s0
; GCN1-NEXT:    v_mov_b32_e32 v1, s1
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_dec_x2 v[0:1], v[2:3]
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_dec_i64:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s0
; GCN2-NEXT:    v_mov_b32_e32 v1, s1
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_dec_x2 v[0:1], v[2:3]
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    s_endpgm
entry:
  %tmp0 = atomicrmw volatile udec_wrap ptr %out, i64 %in seq_cst
  ret void
}

define amdgpu_kernel void @atomic_dec_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GCN1-LABEL: atomic_dec_i64_ret:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN1-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_dec_x2 v[0:1], v[0:1], v[2:3] glc
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    v_mov_b32_e32 v2, s6
; GCN1-NEXT:    v_mov_b32_e32 v3, s7
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_dec_i64_ret:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
; GCN2-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_dec_x2 v[0:1], v[0:1], v[2:3] glc
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    v_mov_b32_e32 v2, s6
; GCN2-NEXT:    v_mov_b32_e32 v3, s7
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %tmp0 = atomicrmw volatile udec_wrap ptr %out, i64 %in seq_cst
  store i64 %tmp0, ptr %out2
  ret void
}

define amdgpu_kernel void @atomic_dec_i64_decr64(ptr %out, i64 %in, i64 %index) {
; GCN1-LABEL: atomic_dec_i64_decr64:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN1-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s6
; GCN1-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN1-NEXT:    s_add_u32 s0, s4, s0
; GCN1-NEXT:    s_addc_u32 s1, s5, s1
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v1, s7
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_dec_x2 v[2:3], v[0:1]
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_dec_i64_decr64:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
; GCN2-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s6
; GCN2-NEXT:    s_lshl_b64 s[0:1], s[0:1], 3
; GCN2-NEXT:    s_add_u32 s0, s4, s0
; GCN2-NEXT:    s_addc_u32 s1, s5, s1
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v1, s7
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_dec_x2 v[2:3], v[0:1]
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %tmp0 = atomicrmw volatile udec_wrap ptr %ptr, i64 %in seq_cst
  ret void
}

define amdgpu_kernel void @atomic_dec_i64_ret_decr64(ptr %out, ptr %out2, i64 %in, i64 %index) {
; GCN1-LABEL: atomic_dec_i64_ret_decr64:
; GCN1:       ; %bb.0: ; %entry
; GCN1-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x9
; GCN1-NEXT:    s_waitcnt lgkmcnt(0)
; GCN1-NEXT:    v_mov_b32_e32 v0, s4
; GCN1-NEXT:    v_mov_b32_e32 v1, s5
; GCN1-NEXT:    s_lshl_b64 s[4:5], s[6:7], 3
; GCN1-NEXT:    s_add_u32 s0, s0, s4
; GCN1-NEXT:    s_addc_u32 s1, s1, s5
; GCN1-NEXT:    v_mov_b32_e32 v3, s1
; GCN1-NEXT:    v_mov_b32_e32 v2, s0
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    flat_atomic_dec_x2 v[0:1], v[2:3], v[0:1] glc
; GCN1-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT:    buffer_wbinvl1_vol
; GCN1-NEXT:    v_mov_b32_e32 v2, s2
; GCN1-NEXT:    v_mov_b32_e32 v3, s3
; GCN1-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN1-NEXT:    s_endpgm
;
; GCN2-LABEL: atomic_dec_i64_ret_decr64:
; GCN2:       ; %bb.0: ; %entry
; GCN2-NEXT:    s_load_dwordx8 s[0:7], s[0:1], 0x24
; GCN2-NEXT:    s_waitcnt lgkmcnt(0)
; GCN2-NEXT:    v_mov_b32_e32 v0, s4
; GCN2-NEXT:    v_mov_b32_e32 v1, s5
; GCN2-NEXT:    s_lshl_b64 s[4:5], s[6:7], 3
; GCN2-NEXT:    s_add_u32 s0, s0, s4
; GCN2-NEXT:    s_addc_u32 s1, s1, s5
; GCN2-NEXT:    v_mov_b32_e32 v3, s1
; GCN2-NEXT:    v_mov_b32_e32 v2, s0
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    flat_atomic_dec_x2 v[0:1], v[2:3], v[0:1] glc
; GCN2-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT:    buffer_wbinvl1_vol
; GCN2-NEXT:    v_mov_b32_e32 v2, s2
; GCN2-NEXT:    v_mov_b32_e32 v3, s3
; GCN2-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; GCN2-NEXT:    s_endpgm
entry:
  %ptr = getelementptr i64, ptr %out, i64 %index
  %tmp0 = atomicrmw volatile udec_wrap ptr %ptr, i64 %in seq_cst
  store i64 %tmp0, ptr %out2
  ret void
}
